MP5921

– 16V, 50A, 1mΩ RDS(ON), HOT-SWAP INTELLI-FUSE SOLUTION

MP5921 Rev. 1.1

www.MonolithicPower.com

16

5/17/2022

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© 2022 MPS. All Rights Reserved.

OPERATION

The

MP5921

is

a

monolithic,

high-side

MOSFET with

1mΩ RDS(ON) ideally suited for

multi-fuse hot-swap applications. The MP5921

can work in standalone operation or can be

controlled by a hot-swap controller for multi-

fuse operation. The MP5921 drives up to 50A of

continuous

current

per

device

at

room

temperature and can reach 60A with air flow.

The MP5921 limits inrush current to the load

when a circuit card is inserted into a live

backplane

power

source,

limiting

the

backplane’s

voltage

drop.

The

MP5921

provides an integrated solution to monitor the

output current and die temperature, eliminating

the need for an external current-sense power

resistor, power MOSFET, and thermal sense

device. It also provides monitored current and

temperature

information

feedback

to

the

processor or controller. The MP5921 limits the

internal MOSFET current by controlling the gate

voltage through the current-limit reference input

and soft-start ramp.

Current Limit at Start-Up

The MP5921 load current is limited by the

current limit reference input and the CS external

resistor. The CS voltage (VSC) is compared with

the current limit reference through an amplifier

to regulate the power FET gate voltage. This

prevents the Intelli-Fuse current from exceeding

the current-limit reference-defined current limit.

The

current-limit

reference

voltage

is

set

through CLREF and clamped low internally

during soft start to allow a controlled and

gradual ramp up of VOUT. Once VOUT is ramped

close to VIN, the current limit reference can be

raised to the full current limit level set by the

CLREF voltage. The power FET gate is fully

enhanced, and the e-fuse is ready to deliver full

power from the input.

To protect the MP5921 from overheating during

start-up, the current limit reference signal has

an internal maximum clamp that depends on

VIN and VOUT (see Figure 2). When VOUT <

80%VIN, the current limit reference is clamped

to

VBE

(around

635mV

with

a

negative

temperature coefficient). When VOUT ≥ 80%VIN,

the maximum current limit reference voltage is

clamped to 1.6V.

If the external CLREF voltage is lower than the

clamp voltage (VCLREF_CLAMP), the actual current

limit reference voltage is determined by the

CLREF voltage.

80%VIN

1.6V

VCLREF_CLAMP

0V

VOUT

0V

t

VBE

Figure 2: CLREF Clamp According to VOUT

The desired start-up current limit (ILIMIT_SS) is a

function of the CS resistor (RCS), start-up

current

sense

gain,

and

CLREF

voltage

(VCLREF_SS). The value of the current sense gain

at start-up is slightly higher than when the

power FET is fully on.

The VOUT power-up ramp time can be estimated

approximately with Equation (1):

OUT

LOAD

LIMIT_SS

IN

RAMP

C

)

I

-

(I

V

t



=

(1)

The VOUT ramp time varies with the load

condition and the output capacitor (COUT) while

adopting the CLREF current limit during start-up.

During start-up, once VCS exceeds VCLREF_SS,

the power FET gate voltage is regulated to hold

the FET current constant. If the power FET

remains on while VOUT remains lower than

90%VIN within the 270ms maximum soft-start

time, the power FET is shut down when the

270ms time ends. If the value of VCLREF_SS is

higher, the power FET start-up instantaneous

loss would be huge, triggering the thermal

shutdown threshold (143°C) before the 270ms

time ends and driving GOK low (see Figure 3).

During start-up, if VOUT is lower than 1/8*VIN

and the power FET current is regulated by VBE

for 2.1ms, the power FET is turned off as a

faulty latched condition, and GOK is pulled low.