MP5921

– 16V, 50A, 1mΩ RDS(ON), HOT-SWAP INTELLI-FUSE SOLUTION

MP5921 Rev. 1.1

www.MonolithicPower.com

24

5/17/2022

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PCB Layout Guidelines

Efficient PCB layout is critical for optimum IC

performance.

A

4-layer

layout

is

strongly

recommended

to

achieve

better

thermal

performance. For best results, refer to Figure

14 and follow the guidelines below.

1.

Place the MP5921 close to the board’s

input

connector

to

minimize

trace

inductance.

2.

Place a small capacitor (CIN, 100nF) close

to the MP5921

’s VIN and GND to minimize

transients, which may occur on the input

supply line.

Transients of several volts can occur easily

when the load current is shut off.

3.

Place a 1µF capacitor as close to VDD3 as

possible.

4.

Keep the high-

current path from the board’s

input to the load (and the return path) close

to each other and in parallel to minimize

loop inductance.

5.

An analog signal ground (AGND) plane is

used locally in the MP5921 and connected

to the PCB power ground planes at a single

point.

6.

Connect the reference ground of all signal

pins

to

the

reference

ground

of

the

controller if the MP5921 cooperates with

the hot-swap controller.

OUT

OUT

OUT

17

16

15

VIN

VIN

VIN

1

2

3

VIN 4

19

20

21

22

23

24

25

26

27

28

5 6 7 8 9 10 11 12 13 14

18 VIN

TVS

VIN

OUT

GND

AGND

CSS

CVDD3

SS

Figure 14: Example of PCB Layout (Placement & Top Layer PCB)

VIN TVS: SMDJ12A

VOUT DIODE: MBRA340T3G for Single MP5921, MBRS540T3G for Paralleling Operation