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MP5921 数据表(PDF) 19 Page - MPS Industries, Inc.

部件名 MP5921
功能描述  16V, 50A, 1mΩ RDS(ON), Hot-Swap Intelli-Fuse Solution
PDF  26 Pages
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制造商  MPSIND [MPS Industries, Inc.]
网页  http://www.mpsind.com/index.html
标志 MPSIND - MPS Industries, Inc.

MP5921 数据表(HTML) 19 Page - MPS Industries, Inc.

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MP5921
– 16V, 50A, 1mΩ RDS(ON), HOT-SWAP INTELLI-FUSE SOLUTION
MP5921 Rev. 1.1
www.MonolithicPower.com
19
5/17/2022
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
The approximate soft-start time is then 1.5ms,
which is the minimum output voltage soft-start
time.
ON/PD Control
ON/PD can be used for on/off control of the
power FET and the pull-down mode of the
output voltage. When ON/PD is used for on/off
control, the power FET is turned on if the
ON/PD voltage is higher than 1.4V. Once the
ON/PD voltage is lower than 1.2V, the power
FET is turned off. If ON/PD is used for VOUT
pull-down mode, the ON/PD voltage must be
clamped at around 1V for more than 80µs. The
MP5921 recognizes 0.8V < ON/PD < 1.2V as a
special state that requires VOUT to be pulled
down.
If ON/PD is used to turn on the power FET,
there is a fixed 1.3ms insertion delay after
VDD3 and VIN pass the UVLO threshold. All
fault
functionality
is
operative
during
the
insertion delay, so the GOK signal is pulled high
if no fault is detected or remains low if a fault is
detected. The power FET remains off until the
insertion delay time ends. At the end of the
insertion delay, ON/PD behaves normally to
turn on the power FET if no fault occurs. The
detail logic is shown in Figure 7 when GOK is
pulled up to the VDD3 voltage.
VIN/
VDD33
ON/PD
ON
SWITCH
GOK
OFF
>1.4 V
Insertion delay
Insertion delay
ON
Figure 7: Power FET On/Off Control when No
Fault Occurs
Once the ON/PD voltage is pulled above 1.4V
and the insertion delay ends, the internal 12μA
current source charges the power FET’s gate.
Once the gate voltage reaches its threshold
(VGSTH), the output voltage rises. The output
voltage rises following the CLREF-controlled
current limit or SS slew rate and output
capacitor.
If the MP5921 works in standalone mode, a
capacitor on ON/PD can be used for automatic
start-up by the internal 4.2µA pull-up current
source. Once the ON/PD voltage reaches its
turn-on threshold, the power FET gate is
charged by the internal 12µA charge pump.
When the ON/PD voltage is set to around 1V,
the MP5921 works in pull-down mode (see
Figure 8). In pull-down mode, when the power
FET is turned off, an integrated 500Ω pull-down
resistor attached to the output discharges the
output voltage after a fixed delay time (2.1ms).
If the ON/PD signal is pulled low directly, pull-
down mode is disabled, and the Intelli-Fuse
output
voltage
is
discharged
through
the
external load.
ON/PD
>1.4 V
Around 1 V
80µs
Internal PD
Enable
PD delay
SWITCH
<0.8 V
1.2 V
0.8 V
FET on
FET off
VOUT
t
Figure 8: VOUT PD Mode
If the MP5921 is controlled by the hot-swap
controller, to achieve power FET on/off control
and VOUT PD mode control, the ON/PD can be
connected as shown in Figure 9. Pull ON/PD up
to VDD3 through a resistor divider (RPD and RON)
from the controller. If ON/PD is set to around 1V
when the hot-swap controller outputs low to turn
off the power FET. RPD can be calculated with
Equation (4):
( )
( )
=
ON
ON
PD
R
N
4.2
μ
-
1
R
2
R
(4)
Where N is the active parallel number. Choose
RON to be 10kΩ. For example, if N is 2, then RPD
can be set to around 22
kΩ.



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