MP6605C

– 4-CHANNEL LOW-SIDE DRIVER WITH I2C INTERFACE

MP6605C Rev. 1.0

MonolithicPower.com

11

7/11/2022

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Normal operation resumes automatically when

the die temperature falls to a safe level.

I2C INTERFACE

The I2C interface is a two-wire, bidirectional

serial interface consisting of a data line (SDA)

and a clock line (SCL). The lines are pulled to a

bus voltage externally when they are idle.

The MP6605C interface is an I2C slave that

supports a maximum clock frequency up to

400kHz.

I2C Update Sequence

The MP6605C requires a start command, valid

I2C address, and data byte. After receiving each

byte, the MP6605C acknowledges the request

by pulling the SDA line low during the high period

of a single clock pulse.

A valid I2C address selects the MP6605C. The

MP6605C performs an update on the falling

edge of the LSB byte.

Start and Stop Commands

The start and stop commands are signaled by

the master device, and they signify the beginning

and the end of the I2C transfer, respectively. A

start (S) command is defined as the SDA signal

transitioning from high to low while SCL is high.

A stop (P) command is defined as the SDA

signal transitioning from low to high while SCL is

high (see Figure 2).

Figure 2: Start and Stop Commands

Address Byte

After the start command, the I2C master sends

an address byte. The address byte consists of a

7-bit address field, and one bit (WR) that

indicates if the transfer is a read (WR = 1) or a

write (WR = 0).

The four LSBs of the address are set by the

A0~A3 input pins, which means that a maximum

of 16 devices can be connected to the same I2C

bus.

The address byte is followed by an acknowledge

bit (see Figure 3).

S

WR

A

8 Bits

Master to Slave

Slave to Master

A = Acknowledge (SDA = Low)

S = Start Command

P = Stop Command

WR (Write = 0;

Read = 1)

A0

A1

A2

A3

0

1

0

Figure 3: Address Byte

Data Byte

After the address is acknowledged, an 8-bit data

byte is sent, followed by an acknowledge bit (see

Figure 4). The state of the WR bit in the address

byte determines if the data is written from the

master to the MP6605C, or if data is read from

the MP6605C.

S

D0

A

8 Bits

Master to Slave

Slave to Master

A = Acknowledge (SDA = Low)

S = Start Condition

P = Stop Condition

D1

D2

D3

S0

x

S1

S2

Slave to Master (WR = 0 (Write)) or

Master to Slave (WR = 1 (Read))

Figure 4: Data Byte

The D0~D3 bits can be written to or read. When

they are written to 1, the corresponding output

bit(s) is driven low. The S0~S2 bits are read-

only, and they correspond to the state of the

S0~S2 input pins.