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MPQ5850 数据表(PDF) 4 Page - MPS Industries, Inc. |
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MPQ5850 数据表(HTML) 4 Page - MPS Industries, Inc. |
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4 / 29 page ![]() MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 4 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description 1 EN/UVLO Enable pin. Pull EN below the specified threshold (1V) to shut down the chip. Pull EN above the threshold (1.2V) to enable the chip. A resistor divider connected between EN/UVLO and SOURCE can be used to raise the under-voltage lockout (UVLO) threshold. Do not float the EN/UVLO pin, and connect it to DRAIN if the shutdown feature not used. 2 PG Open-drain power good pin. The PG pin asserts low if the device is disabled, the reservoir supply is out of regulation, or if the fast pull-up path is active for longer than 17 μs. Float PG or connect it to GND if it is not used. 3 GND Ground connection of the device. Connect GND to the ground plane of the board. 4 SW Switch node of internal boost regulator. Connect an inductor between the SW and DRAIN pins. 5 RES Reservoir supply. RES is the power supply for the external N-channel MOSFET gate driver. Connect a minimum 1μF ceramic capacitor between the RES and DRAIN pins. 6 DRAIN Drain connection. Connect the DRAIN pin to the drain of the external power MOSFET. DRAIN is the power supply of the internal circuitry, and also controls the MOSFET ’s gate voltage. Connect a minimum 4.7μF capacitor from DRAIN to ground, and place this capacitor as close as possible to the device. 7 GATE Gate connection. Connect the GATE pin to the gate of the external power MOSFET. 8 SOURCE Source connection. Connect the SOURCE pin to the source of the external power MOSFET. The voltage sensed on this pin works with the DRAIN voltage to control the MOSFET gate. ABSOLUTE MAXIMUM RATINGS (1) SOURCE, EN/UVLO..................... -36V to +42V DRAIN ......................................... -0.3V to +42V DRAIN - SOURCE .......................... -2V to +52V GATE - SOURCE ........................ -0.3V to +13V RES .................................. -0.3V to VDRAIN + 13V SW............................................... -0.3V to +57V PG ................................................. -0.3V to +6V Continuous power dissipation (TA = 25°C) (2) TSOT23-8 (2mmx3mm) .............................1.5W Junction temperature ............................... 150°C Lead temperature .................................... 260°C Electrostatic Discharge (ESD) Ratings Human body model (HBM) ................ Class 2 (3) Charged device model (CDM) .......Class C2b (4) Recommended Operating Conditions Supply voltage (VIN) ........................ 3.3V to 36V Operating junction temp (TJ) .... -40°C to +150°C Thermal Resistance θJA θJC TSOT23-8 (2mmx3mm) JESD51-7 (5) ........................... 85 ...... 20... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ (MAX), the junction-to- ambient thermal resistance, θ JA, and the ambient temperature, TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX) - TA)/ θJA. Exceeding the maximum allowable power dissipation can produce an excessive die temperature, and the device may go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) Per AEC-Q100-002. 4) Per AEC-Q100-011. 5) Measured on JESD51-7, 4-layer PCB. The values given in this table are only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD51-7, and simulated on a specified JEDEC board. They do not represent the performance obtained in an actual application. |
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