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MPQ5850 数据表(PDF) 25 Page - MPS Industries, Inc. |
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MPQ5850 数据表(HTML) 25 Page - MPS Industries, Inc. |
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25 / 29 page ![]() MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 25 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. frequency. CLOAD can be estimated with Equation (9): AC R LOAD LOAD AC R 4 V V CI 4 V f V − (9) Where VAC is the SOURCE voltage ripple amplitude (in V), f is the ripple frequency (in Hz), CLOAD is the capacitance of the electrolytic capacitor (in F), and ILOAD is the load current (in A). If the ripple voltage (VR) is below 2V, f is 5kHz, VAC is 3V (6VPP), and ILOAD is 5A, then CLOAD is 417 μF. Selecting the TVS Diode The MPQ5850 can be damaged by the negative pulse on the SOURCE pin, since the voltage of the SOURCE pin is limited to -36V. Connect a TVS diode between SOURCE and GND to protect the part. The SMBJ24CA is recommended, as it can protect the MPQ5850 from negative pulses and over-voltage conditions. PCB Layout Guidelines (8) An optimized PCB layout is very important for proper operation. A four-layer layout is strongly recommended to improve thermal performance. For the best results, refer to Figure 3 and follow the guidelines below: 1. Place SW close to the device with short, direct, and wide traces. 2. Use large copper areas to minimize conduction loss and thermal stress. 3. Place the ceramic input capacitors as close to the IN and GND pins as possible to minimize high-frequency noise. 4. Route SW away from sensitive analog areas. 5. Use multiple vias to connect the power planes to internal layer. Note: 8) The recommended PCB layout is based on the circuit in Figure 4 on page 26. Top Silk and Top Layer Mid-Layer 1 Mid-Layer 2 Bottom Layer and Bottom Silk Figure 3: Recommended PCB Layout |
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