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WM8569SEDS/V 数据表(PDF) 17 Page - Wolfson Microelectronics plc

部件名 WM8569SEDS/V
功能描述  24-bit, 192kHz Stereo CODEC with Volume Control
PDF  36 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8569SEDS/V 数据表(HTML) 17 Page - Wolfson Microelectronics plc

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Production Data
WM8569
w
PD Rev 4.0 June 2006
17
DIGITAL AUDIO INTERFACE
MASTER AND SLAVE MODES
The audio interface operates in either Slave or Master mode, selectable using the DACMS and
ADCMS control bits. In both Master and Slave modes DIN is always an input to the WM8569 and
DOUT is always an output. The default is Slave mode.
In Slave mode, DACLRC, ADCLRC, DACBCLK and ADCBCLK are inputs to the WM8569 (Figure
11). DIN and DACLRC are sampled by the WM8569 on the rising edge of DACBCLK. ADC data is
output on DOUT and changes on the falling edge of ADCBCLK.
By setting the control bit DACBCP the polarity of DACBCLK may be reversed so that DIN is sampled
on the falling edge of DACBCLK. By setting the control bit ADCBCP, the polarity of ADCBCLK may
be reversed so that DOUT changes on the rising edge of ADCBCLK.
Figure 11 Slave Mode
In Master mode, DACLRC, ADCLRC, DACBCLK and ADCBCLK are outputs from the WM8569
(Figure 12). DACLRC, ADCLRC, DACBCLK and ADCBCLK are generated by the WM8569. DIN is
sampled by the WM8569 on the rising edge of DACBCLK so the controller must output DAC data
that changes on the falling edge of DACBCLK. ADC data is output on DOUT and changes on the
falling edge of ADCBCLK.
By setting the control bit DACBCP the polarity of DACBCLK may be reversed so that DIN is sampled
on the falling edge of DACBCLK. By setting the control bit ADCBCP, the polarity of ADCBCLK may
be reversed so that DOUT changes on the rising edge of ADCBCLK.
Figure 12 Master Mode



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