Production Data

WM8569

w

PD Rev 4.0 June 2006

19

RIGHT JUSTIFIED MODE

In right justified mode, the LSB of DIN is sampled by the WM8569 on the rising edge of DACBCLK

preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the

falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of

ADCBCLK. LRC are high during the left samples and low during the right samples (Figure 14).

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN1/2/3/

DOUT

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

Figure 14 Right Justified Mode Timing Diagram

I

In I

following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the

first falling edge of ADCBCLK following an ADCLRC transition and may be sampled on the rising

edge of ADCBCLK. LRC are low during the left samples and high during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN1/2/3/

DOUT

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

1 BCLK

1 BCLK

Figure 15 I

DSP MODE A

In DSP mode A, the MSB of DAC left channel data is sampled by the WM8569 on the second rising

edge on DACBCLK following a DACLRC rising edge. DAC right channel follows DAC left channel

(Figure 16).

Figure 16 DSP Mode A Timing Diagram – DAC Data Input