WM8569

Production Data

w

PD Rev 4.0 June 2006

20

The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of

ADCBCLK following a low to high ADCLRC transition and may be sampled on the rising edge of

ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 17)

ADCLRC

ADCBCLK

DOUT

Input Word Length (IWL)

1/fs

LEFT CHANNEL

n

2

1

n-1

LSB

MSB

n

2

1

n-1

RIGHT CHANNEL

NO VALID DATA

1 BCLK

1 BCLK

Figure 17 DSP Mode A Timing Diagram – ADC Data Output

DSP MODE B

In DSP mode B, the MSB of DAC left channel data is sampled by the WM8569 on the first

DACBCLK rising edge following a DACLRC rising edge. (Figure 18).

Figure 18 DSP Mode B Timing Diagram – DAC Data Input

The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of

ADCBCLK as the low to high ADCLRC transition and may be sampled on the rising edge of

ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 19).

ADCLRC

BCK

DOUT

Input Word Length (IWL)

1/fs

LEFT CHANNEL

n

2

1

n-1

LSB

MSB

n

2

1

n-1

RIGHT CHANNEL

NO VALID DATA

1

Figure 19 DSP Mode B Timing Diagram – ADC Data Output