WM8772SEDSSLASHV datasheet(56/73 Pages) WOLFSON

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WM8772EFT – 32 LEAD TQFP

Production Data

PD Rev 4.2 October 2005

DACLRC

DACBCLK

DIN1

Input Word Length (IWL)

1/fs

CHANNEL 1

LEFT

n-1

LSB

MSB

n-1

CHANNEL 1

RIGHT

CHANNEL 2

LEFT

n-1

CHANNEL 3

RIGHT

NO VALID DATA

Figure 55 DSP Mode Audio Interface - Mode B Master, DAC

The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of

ADCBCLK as the low to high ADCLRC transition and may be sampled on the rising edge of

ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 56).

Figure 56 DSP Mode Audio Interface - Mode A Slave, ADC

ADCLRC

BCK

DOUT

Input Word Length (IWL)

1/fs

LEFT CHANNEL

n-1

LSB

MSB

n-1

RIGHT CHANNEL

NO VALID DATA

Figure 57 DSP Mode Audio Interface - Mode B Master, ADC

In both DSP mode A and mode B , DACL1 is always sent first, followed immediately by DACR1 and

the data words for the other 6 channels. No BCLK edges are allowed between the data words. The

word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right.

WM8772SEDS/V 数据表(PDF) 56 Page - Wolfson Microelectronics plc

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