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WM8772SEDS/V 数据表(PDF) 18 Page - Wolfson Microelectronics plc |
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WM8772SEDS/V 数据表(HTML) 18 Page - Wolfson Microelectronics plc |
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18 / 73 page  WM8772EDS – 28 LEAD SSOP Production Data w PD Rev 4.2 October 2005 18 DIGITAL AUDIO INTERFACE – SLAVE MODE LRC DOUT BCLK DIN1/2/3 WM8772 CODEC DSP ENCODER/ DECODER 3 Figure 16 Audio Interface – Slave Mode BCLK LRC t BCH t BCL t BCY DIN1/2/3 DOUT t LRSU t DS t LRH t DH t DD Figure 17 Digital Audio Data Timing – Slave Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRC set-up time to BCLK rising edge tLRSU 10 ns LRC hold time from BCLK rising edge tLRH 10 ns DIN1/2/3 set-up time to BCLK rising edge tDS 10 ns DIN1/2/3 hold time from BCLK rising edge tDH 10 ns |
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