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AT89C5131A-RDTIL 数据表(PDF) 92 Page - ATMEL Corporation |
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AT89C5131A-RDTIL 数据表(HTML) 92 Page - ATMEL Corporation |
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92 / 185 page  92 AT89C5131A-L 4338E–USB–06/06 Functional Description Figure 42 shows a detailed structure of the SPI module. Figure 42. SPI Module Block Diagram Operating Modes The Serial Peripheral Interface can be configured as one of the two modes: Master mode or Slave mode. The configuration and initialization of the SPI module is made through one register: • The Serial Peripheral CONtrol register (SPCON) Once the SPI is configured, the data exchange is made using: •SPCON • The Serial Peripheral STAtus register (SPSTA) • The Serial Peripheral DATa register (SPDAT) During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam- pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities. When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 43). Shift Register 0 1 2 3 4 5 6 7 Internal Bus Pin Control Logic MISO MOSI SCK M S Clock Logic Clock Divider Clock Select /4 /64 /128 SPI Interrupt Request 8-bit bus 1-bit signal SS FCLK PERIPH /32 /8 /16 Receive Data Register SPDAT SPI Control SPSTA CPHA SPR0 SPR1 CPOL MSTR SSDIS SPEN SPR2 SPCON WCOL MODF SPIF -- - - SSERR |
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