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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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AT89C5131A-RDTIL 数据表(PDF) 168 Page - ATMEL Corporation |
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AT89C5131A-RDTIL 数据表(HTML) 168 Page - ATMEL Corporation |
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168 / 185 page  168 AT89C5131A-L 4338E–USB–06/06 External Data Memory Read Cycle Serial Port Timing - Shift Register Mode Table 120. Symbol Description (F = 40 MHz) Table 121. AC Parameters for a Fix Clock (F = 40 MHz) Table 122. AC Parameters for a Variable Clock ALE PSEN RD PORT 0 PORT 2 A0-A7 DATA IN ADDRESS OR SFR-P2 TAVWL TLLWL TRLAZ ADDRESS A8-A15 OR SFR P2 TRHDZ TWHLH T RLRH TLLDV TRHDX TLLAX TAVDV Symbol Parameter TXLXL Serial port clock cycle time TQVHX Output data set-up to clock rising edge TXHQX Output data hold after clock rising edge TXHDX Input data hold after clock rising edge TXHDV Clock rising edge to input data valid Symbol Min Max Units TXLXL 300 ns TQVHX 200 ns TXHQX 30 ns TXHDX 0ns TXHDV 117 ns Symbol Type Standard Clock X2 Clock X Parameter for -M Range Units T XLXL Min 12 T 6 T ns T QVHX Min 10 T - x 5 T - x 50 ns T XHQX Min 2 T - x T - x 20 ns T XHDX Min x x 0 ns T XHDV Max 10 T - x 5 T- x 133 ns |
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