 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AMC131M01DFMR 数据表(PDF) 32 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AMC131M01DFMR 数据表(HTML) 32 Page - Texas Instruments |
|
|
32 / 81 page  POR sequence DVDD supply present? Yes No No Yes DRDY high? Configure registers: CLK_DIV[1:0] DCDC_FREQ[3:0] All other configurations as needed Set DCDC_EN = 1b No Yes External clock provided at CLKIN pin? Send NULL command or RREG command to read from STATUS register No Yes SEC_FAIL status bit is low? Power supply DVDD on primary (low) side not valid Power supply HLDO_OUT on secondary (high) side not valid ADC is generating conversion data No Yes DRDY pin or DRDY status bit is low? ADC conversion is ongoing New, valid conversion data is available to read via SPI DVDD supply present? No Yes Power down Device is still powered Device was powered down No Yes Digital filter is settled? ADC data is not settled Figure 8-14. Flow Diagram for Start-Up Procedure at Power-Up AMC131M01 SBASA57 – SEPTEMBER 2023 www.ti.com 32 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AMC131M01 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
