AD8571/AD8572/AD8574

Rev. B | Page 16 of 24

Thus, the offset voltages of both the primary and nulling

amplifiers are reduced by the

input offset voltage from several millivolts down to an effective

input offset voltage of submicrovolts. This autocorrection

scheme makes the AD857x family of amplifiers extremely

precise.

HIGH GAIN, CMRR, PSRR

Common-mode and power supply rejection are indications of

the amount of offset voltage an amplifier has as a result of a

change in its input common-mode or power supply voltages. As

shown in the Amplification Phase section, the autocorrection

architecture of the AD857x allows it to effectively minimize

offset voltages. The technique also corrects for offset errors

caused by common-mode voltage swings and power supply

variations. This results in superb CMRR and PSRR figures in

excess of 130 dB. Because the autocorrection occurs continu-

ously, these figures can be maintained across the entire

temperature range of the device, from −40°C to +125°C.

MAXIMIZING PERFORMANCE THROUGH

PROPER LAYOUT

To achieve the maximum performance of the extremely high

input impedance and low offset voltage of the AD857x, care

should be taken in the circuit board layout. The PC board

surface must remain clean and free of moisture to avoid leakage

currents between adjacent traces. Surface coating of the circuit

board reduces surface moisture and provides a humidity barrier,

reducing parasitic resistance on the board. The use of guard rings

around the amplifier inputs further reduces leakage currents.

Figure 52 shows how the guard ring should be configured and

Figure 53 shows the top view of how a surface mount layout can

be arranged. The guard ring does not need to be a specific width,

but it should form a continuous loop around both inputs. By

setting the guard ring voltage equal to the voltage at the nonin-

verting input, parasitic capacitance is minimized as well. For

further reduction of leakage currents, components can be

mounted to the PC board using Teflon® standoff insulators.

AD8572

AD8572

V

IN

AD8572

Figure 52. Guard Ring Layout and Connections to Reduce

PC Board Leakage Currents

V–

V+

GUARD

RING

R1

R2

R2

R1

AD8572

GUARD

RING

Figure 53. Top View of AD8572 SOIC Layout with Guard Rings

Other potential sources of offset error are thermoelectric

voltages on the circuit board. This voltage, also called Seebeck

voltage, occurs at the junction of two dissimilar metals and is

proportional to the temperature of the junction. The most

common metallic junctions on a circuit board are solder-to-

board trace and solder-to-component lead. Figure 54 shows a

cross-section view of the thermal voltage error sources. When

the temperature of the PC board at one end of the component

Seebeck voltages are not equal, resulting in a thermal voltage error.

This thermocouple error can be reduced by using dummy

components to match the thermoelectric error source. Placing

the dummy component as close as possible to its partner ensures

both Seebeck voltages are equal, thus canceling the thermocouple

error. Maintaining a constant ambient temperature on the

circuit board further reduces this error. The use of a ground

plane helps distribute heat throughout the board and also

reduces EMI noise pickup.

SURFACE MOUNT

COMPONENT

COMPONENT

LEAD

SOLDER

PC BOARD

COPPER

TRACE

+

–

+

–

+

+

–

–

Figure 54. Mismatch in Seebeck Voltages Causes

a Thermoelectric Voltage Error

AD8571/AD8572/

AD8574

R1

Figure 55. Using Dummy Components to Cancel

Thermoelectric Voltage Errors