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ADL5330ACPZ-R2 数据表(PDF) 13 Page - Analog Devices

部件名 ADL5330ACPZ-R2
功能描述  10 MHz to 3 GHz VGA with 60 dB Gain Control Range
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL5330ACPZ-R2 数据表(HTML) 13 Page - Analog Devices

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ADL5330
Rev. A | Page 13 of 24
APPLICATIONS
BASIC CONNECTIONS
Figure 32 shows the basic connections for operating the
ADL5330. There are two positive supplies, VPS1 and VPS2,
which must be connected to the same potential. Both COM1
and COM2 (common pins) should be connected to a low
impedance ground plane.
A power supply voltage between 4.75 V and 5.25 V should be
applied to VPS1 and VPS2. Decoupling capacitors with 100 pF
and 0.1 μF power supplies should be connected close to each
power supply pin. The VPS2 pins (Pin 18 through Pin 22) can
share a pair of decoupling capacitors because of their proximity
to each other.
The outputs of the ADL5330, OPHI and OPLO, are open
collectors that need to be pulled up to the positive supply with
120 nH RF chokes. The ac-coupling capacitors and the RF
chokes are the principle limitations for operation at low
frequencies. For example, to operate down to 1 MHz, 0.1 μF ac-
coupling capacitors and 1.5 μH RF chokes should be used. Note
that in some circumstances, the use of substantially larger
inductor values results in oscillations.
Since the differential outputs are biased to the positive supply,
ac-coupling capacitors, preferably 100 pF, are needed between
the ADL5330 outputs and the next stage in the system.
Similarly, the INHI and INLO input pins are at bias voltages of
about 3.3 V above ground.
The nominal input and output impedance looking into each
individual RF input/output pin is 25 Ω. Consequently, the
differential impedance is 50 Ω.
To enable the ADL5330, the ENBL pin must be pulled high.
Taking ENBL low puts the ADL5330 in sleep mode, reducing
current consumption to 250 μA at ambient. The voltage on
ENBL must be greater than 1.7 V to enable the device. When
enabled, the device draws 100 mA at low gain to 215 mA at
maximum gain.
INHI
C13
100pF
C11
100pF
C12
0.1
μF
C10
1nF
C9
1nF
INLO
COM1
VPS1
VPS1
COM1
C14
100pF
OPHI
C5
100pF
OPLO
COM2
VPS2
VPS2
COM2
C6
100pF
C7
100pF
C8
0.1
μF
C1
0.1
μF
C2
100pF
C16
100pF
C12
0.1
μF
VPOS
GAIN
RF INPUT
RF OUTPUT
VPOS
VPOS
VPOS
C3
0.1
μF
C4
100pF
VPOS
L2
120nH
L1
120nH
ADL5330
Figure 32. Basic Connections



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