DAP002 datasheet(13/23 Pages) STMICROELECTRONICS

13 / 23 page

connecting DC-LIM to VREF (half duty cycle op-

tion), Dx will be set approximately at:

≅

⋅ RT + 260

(11)

and the output switching frequency will be halved

with respect to the oscillator one because an in-

ternal T flip-flop (see block diagram) is activated.

Fig. 31 shows the operation.

The half duty cycle option speeds up the dis-

charge of the timing capacitor CT (in order to get

duty cycles as close to 50% as possible) so the

oscillator frequency - with the same timing compo-

nents will be slightly higher.

Pin 16. S-BY (Standby Function). The resistor RB,

along with RA, sets the operating frequency of the

oscillator in normal operation (fosc). In fact, as long

as the STANDBY signal is high, the pin is inter-

nally connected to the reference voltage VREF by

a N-channel FET (see fig. 32), so the timing ca-

pacitor CT is charged through RA and RB. When

the STANDBY signal goes low the N-channel FET

is turned off and the pin becomes floating. RB is

D97IN502

DIS

DISABLE

UVLO

2.5V

DISABLE

SIGNAL

Figure 30. Disable (Latched).

V15=GND

V5=V13=GND

V15=VREF

V5=V13=GND

V10

DX =

tc + td

DX =

2 ·tc + td

D97IN498

Figure 31. Half duty cycle option.

2.5

2.5/4

STANDBY

10V

LEVEL SHIFT

COMP

VREF

ST-BY

RCT

LOW

HIGH

STANDBY

D97IN752B

VT1

2.5V

VT2

VCOMP

ISEN

DRIVER

OUT

STANDBY BLOCK

Figure 32. Standby function internal schematic and operation.

L5991 - L5991A

13/23

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