AD8061/AD8062/AD8063

Rev. D | Page 15 of 20

TIME (ns)

2.0

0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

4

8

12

16

20

24

28

32

2V TO 3V STEP

2.1V TO 3.1V STEP

2.2V TO 3.2V STEP

2.3V TO 3.3V STEP

2.4V TO 3.4V STEP

Figure 47. Output Rising Edge for 1 V Step at

As the saturation point of the output stage is approached, the

output signal shows increasing amounts of compression and

clipping. As in the input headroom case, the higher frequency

signals require a bit more headroom than lower frequency

signals. Figure 16, Figure 17, and Figure 18 illustrate this point,

plotting typical distortion vs. output amplitude and bias for

gains of 2 and 5.

OVERLOAD BEHAVIOR AND RECOVERY

Input

The specified input common-mode voltage of the AD806x

is −200 mV below the negative supply to within 1.8 V of

the positive supply. Exceeding the top limit results in lower

bandwidth and increased settling time as seen in Figure 46

and Figure 47. Pushing the input voltage of a unity-gain

follower beyond 1.6 V within the positive supply leads to the

behavior shown in Figure 48—an increasing amount of output

error and much increased settling time. Recovery time from

input voltages 1.6 V or closer to the positive supply is approxi-

mately 35 ns, which is limited by the settling artifacts caused by

transistors in the input stage coming out of saturation.

The AD806x family does not exhibit phase reversal, even for

input voltages beyond the voltage supply rails. Going more

than 0.6 V beyond the power supplies will turn on protection

diodes at the input stage, which will greatly increase the device’s

current draw.

TIME (ns)

2.1

0

2.3

100

VOLTAGE STEP

FROM 2.4V TO 3.4V

2.5

2.7

2.9

3.1

3.3

3.5

3.7

VOLTAGE STEP

FROM 2.4V TO 3.6V

VOLTAGE STEP

FROM 2.4V TO 3.8V,

4V AND 5V

200

300

400

500

600

Figure 48. Pulse Response for G = 1 Follower,

Input Step Overloading the Input Stage

Output

Output overload recovery is typically within 40 ns after the

amplifier’s input is brought to a nonoverloading value. Figure 49

shows output recovery transients for the amplifier recovering

from a saturated output from the top and bottom supplies to a

point at midsupply.

TIME (ns)

OUTPUT VOLTAGE

5V TO 2.5V

0.2

0.6

1.0

1.4

1.8

2.2

2.6

3.0

3.4

3.8

4.2

4.6

5.0

10

20

30

40

50

60

70

OUTPUT VOLTAGE

0V TO 2.5V

INPUT VOLTAGE

EDGES

R

5V

2.5V

R

–

–

0

CAPACITIVE LOAD DRIVE

The AD806x family is optimized for bandwidth and speed, not

for driving capacitive loads. Output capacitance creates a pole

in the amplifier’s feedback path, leading to excessive peaking

and potential oscillation. If dealing with load capacitance is a

requirement of the application, the two strategies to consider

are as follows:

1.

Use a small resistor in series with the amplifier’s output and

the load capacitance.

2.

Reduce the bandwidth of the amplifier’s feedback loop by

increasing the overall noise gain.