AD8332ACP-R2 datasheet(33/40 Pages) AD

33 / 40 page

AD8331/AD8332/AD8334

Rev. E | Page 33 of 40

OPTIONAL INPUT OVERLOAD PROTECTION

Applications in which high transients are applied to the LNA

input can benefit from the use of clamp diodes. A pair of back-

to-back Schottky diodes can reduce these transients to manageable

levels. Figure 88 illustrates how such a diode-protection scheme

can be connected.

LON

VPSL

INH

COMM

ENBL

0.1µF

RSH

CFB

RFB

CSH

OPTIONAL

SCHOTTKY

OVERLOAD

CLAMP

BAS40-04

Figure 88. Input Overload Clamping

When selecting overload protection, the important parameters

are forward and reverse voltages and trr (or τrr). The Infineon

BAS40-04 series shown in Figure 88 has a τrr of 100 ps and VF of

310 mV at 1 mA. Many variations of these specifications can be

found in vendor catalogs.

LAYOUT, GROUNDING, AND BYPASSING

Due to their excellent high frequency characteristics, these

devices are sensitive to their PCB environment. Realizing

expected performance requires attention to detail critical to

good high speed board design.

A multilayer board with power and ground planes is

recommended with blank areas in the signal layers filled with

ground plane. Be certain that the power and ground pins

provided for robust power distribution to the device are

connected. Decouple the power supply pins with surface-mount

capacitors as close as possible to each pin to minimize impedance

paths to ground. Decouple the LNA power pins from the VGA

supply using ferrite beads. Together with the capacitors, ferrite

beads eliminate undesired high frequencies without reducing

the headroom. Use a larger value capacitor for every 10 chips to

20 chips to decouple residual low frequency noise. To minimize

voltage drops, use a 5 V regulator for the VGA array.

Several critical LNA areas require special care. The LON and

LOP output traces must be as short as possible before connecting to

the coupling capacitors connected to Pin VIN and Pin VIP. RFB

must be placed near the LON pin as well. Resistors must be

placed as close as possible to the VGA output pins, VOL and

VOH, to mitigate loading effects of connecting traces. Values

are discussed in the Output Decoupling section.

Signal traces must be short and direct to avoid parasitic effects.

Wherever there are complementary signals, symmetrical layout

should be employed to maintain waveform balance. PCB traces

should be kept adjacent when running differential signals over a

long distance.

MULTIPLE INPUT MATCHING

Matching of multiple sources with dissimilar impedances can be

accomplished as shown in Figure 90. A relay and low supply

voltage analog switch can be used to select between multiple

sources and their associated feedback resistors. An ADG736

dual SPDT switch is shown in this example; however, multiple

switches are also available and users are referred to the Analog

Devices Selection Guide for switches and multiplexers.

DISABLING THE LNA

Where accessible, connection of the LNA enable pin to ground

powers down the LNA, resulting in a current reduction of about

half. In this mode, the LNA input and output pins can be left

unconnected; however, the power must be connected to all the

supply pins for the disabling circuit to function. Figure 89

illustrates the connections using an AD8331 as an example.

COMM

VIP

LOP

COML

LMD

LON

VPSL

INH

COMM

ENBV

ENBL

GAIN

0.1µF

HILO

CFB

0.018µF

VOH

VOL

VOUT

VPOS

VCM

RCLMP

VIN

0.1µF

AD8331

MODE

GAIN

MODE

VCM

HILO

VIN

RCLMP

Figure 89. Disabling the LNA

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