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AT89C51AC3-RDTUM 数据表(PDF) 25 Page - ATMEL Corporation |
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AT89C51AC3-RDTUM 数据表(HTML) 25 Page - ATMEL Corporation |
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25 / 143 page  25 AT89C51AC3 4383B–8051–01/05 Registers Table 6. PSW Register PSW (S:8Eh) Program Status Word Register Reset Value = 0000 0000b Table 7. AUXR Register AUXR (S:8Eh) Auxiliary Register 76 543 210 CY AC F0 RS1 RS0 OV F1 P Bit Number Bit Mnemonic Description 7CY Carry Flag Carry out from bit 1 of ALU operands. 6AC Auxiliary Carry Flag Carry out from bit 1 of addition operands. 5F0 User Definable Flag 0. 4-3 RS1:0 Register Bank Select Bits Refer to Table 4 for bits description. 2OV Overflow Flag Overflow set by arithmetic operations. 1F1 User Definable Flag 1 0P Parity Bit Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s. 76 543 210 - - M0 XRS2 XRS1 XRS0 EXTRAM A0 Bit Number Bit Mnemonic Description 7-6 - Reserved The value read from these bits are indeterminate. Do not set this bit. 5M0 Stretch MOVX control: the RD/ and the WR/ pulse length is increased according to the value of M0. M0 Pulse length in clock period 0 6 1 30 |
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