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TDA7513

strength of the narrow-band signal is higher than an internally defined threshold. The fieldstrength signal

must be low-passed to remove audio content and this is done by use of the capacitor at pin #SMETERTC

with an I2C bus programmable internal resistor. The value of the capacitor is determined for correct FM

operation; the value of the internal resistor for AM is selectable in order to make the AM time constant

suitable for AM operation.

A station detection function is provided for easy seek stop operation. The fieldstrength signal is compared

with a programmable threshold and the result (logic '1' if the current station strength is higher than the

threshold) is combined by an AND gate with the IF counter output (logic '1' if the current channel is cen-

tered within a programmable window around the desired frequency). The result is available on pin #SD for

direct connection to the microprocessor.

4.3 PLL and IF Counter Section

The IC contains a frequency synthesizer and a loop filter for the radio tuning system. Only one VCO is

required to build a complete PLL system for FM and AM upconversion. For auto search stop operation an

IF counter system is available.

PLL Frequency Synthesizer Block

The counter works in a two stages configuration. The first stage is a swallow counter with a two-modulus

(32/33) precounter. The second stage is an 11-bit programmable counter. The circuit receives the scaling

factors for the programmable counters and the values of the reference frequency via I2C bus. The refer-

ence frequency is generated by an adjustable internal (XTAL) oscillator followed by the reference divider.

The reference and step-frequencies are independently selectable (RC, PC). The phase-frequency detec-

tor outputs switches the programmable current source. The loop filter integrates the latter to a DC voltage.

The current source values is programmable with 6 bits received via I2C bus (A, B, CURRH, LPF). To min-

imize the noise induced by the digital part of the system, a special guard area is implemented. The loop

gain can be adjusted for different conditions by setting the current values of the chargepump generator.

Frequency Generation for Phase Comparison

The VCO signal is fed to a two-modulus counter (32/33) prescaler, which is controlled by a 5-bit divider

(A). A 5-bit register (PC0 to PC4) controls this divider. The output of the prescaler is connected to an 11-

bit divider (B), controlled by an 11-bit PC register (PC5 to PC15).

The following expressions relate the divider output frequency (fSYN, forced by the loop to equal the refer-

ence frequency at the phase comparator input fREF) to the VCO frequency (fVCO) and to the crystal oscil-

lator frequency (fXTAL):

fXTAL = (R+1) x fREF

fVCO = [33 x A + (B + 1 - A) x 32] x fREF

fVCO = (32 x B + A + 32) x fREF

Important: For correct operation: A

≤32; B ≥A

Three State Phase Comparator

The phase comparator generates a phase error signal according to phase difference between fSYN and

fREF. This phase error signal drives the charge pump current generator.

Charge Pump Current Generator

This system generates correction current pulses with a polarity and a duration dictated by the phase error

signal. The current absolute values are programmable through register A for high current and register B

for low current.

The charge pump operates in high current mode when the phase difference between between fSYN and

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