TDA7513 datasheet(20/58 Pages) STMICROELECTRONICS

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TDA7513

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fREF is high. The switch back to low current mode can be done either automatically as a function of the

inlock detector output (setting bit LDENA to "1") or via software.

After reaching a phase difference equivalent to 10-40 ns (programmable) and a delay multiple of 1/fREF,

the chargepump is forced in low current mode. A new PLL divider programming by I2C bus will switch the

chargepump into high current mode.

A few programmable phase errors (D0, D1) are available for inlock detection. The count of detected inlock

informations to release the inlock signal is adjustable (D2, D3), to avoid switching to low current during a

frequency jump.

Low Noise CMOS Op-amp

An internal voltage divider at pin #LFREF is connected to the positive input of the low noise op-amp. The

charge pump output is connected to the negative input. This internal amplifier in cooperation with external

components provides the active loop filter. Only one loop filter connection is provided because the same

reference frequency is used for both AM and FM operation. The pin #LFHC is connected in such a way

as to partially shunt the loop filter in order to decrease the time constant of the filter itself during jumps with

high current mode activated.

IF Counter Block

The input signal for FM and AM has the same structure although FM IF is measured at IF1 (10.7MHz) and

AM IF is measured at IF2 (450kHz). The degree of integration is adjustable to up to eight different mea-

suring cycle times. The tolerance of the accepted count value is adjustable to reach the optimum compro-

mise between search speed and evaluation precision.

T center frequency of the measured count value is adjustable to fit the IF-filter tolerance.

The IF-Counter Mode

The IF counter works in 2 modes controlled by the IFCM register.

Sampling Timer

A 14-bit programmable (IRC) sampling timer generates the gate signal for the main counter. In FM mode

a 6.25kHz frequency reference is generated for this purpose, whereas in AM mode this reference be-

comes 1kHz. These reference frequencies are further divided to generate the measurement time windows

(160us - 320

µs ... 20.48ms for FM, 1ms - 2ms … 128ms for AM).

Intermediate Frequency Main Counter

This counter is a 11 - 21-bit synchronous autoreload down counter. Five bits (CF) are programmable to

allow the adjustment to the peak of the IF-filter response. The counter length is automatically adjusted to

the chosen sampling time and counter mode (FM, AM).

The IF counter is also used to automatically perform the stereo decoder 456kHz VCO frequency adjust-

ment.

At the start the counter will be loaded with a value equivalent to the expected number of zero-crossing in

the sampling time window (tSample x fIF ). If the correct frequency is applied to the IF counter input, at the

end of the sampling time the main counter will have either a 0h state or a 1FFFFFh state stored.

A deviation from the expected IF will result in a difference of the counter final state from either of these

values. The counter final state is then compared to either 0h or 1FFFFFh minus a number of LSB's deter-

mined by the acceptable frequency window programming (EW).

If the comparison result is good the IF counter output changes from LOW to HIGH and is made available

outside at the pin #SD (after a NAND operation with the signal strength evaluation circuit). The following

relationships apply:

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