TDA7513 datasheet(27/58 Pages) STMICROELECTRONICS

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TDA7513

AF Search Control

The device is supplied with several functionality to support AF-checks using the stereodecoder. As already

mentioned before the high ohmic mute feature at the stereo decoder input avoids any clicks during the

jump condition.

It is possible at the same time to evaluate the noise- and multipath-content of the alternate frequency by

using the Quality detector output. During this time the multipath detector is automatically switched to a

small time constant.

One dedicated pin (#RDSMUTE) is provided in order to separate the audioprocessor-mute and stereode-

coder AF-functions.

4.9 I2C-Bus Interface

I2C bus protocol is supported. This protocol defines any device that sends data onto the bus as a trans-

mitter, and the receiving device as the receiver.

The device that controls the transfer is a master and device being controlled is the slave. The master will

always initiate data transfer and provide the clock to transmit or receive operations. The present device

always acts as slave, both in transmission and in reception mode.

Data Transition

Data transition on the SDA line must only occur when the clock SCL is LOW. SDA transitions while SCL

is HIGH will be interpreted as START or STOP condition.

Start Condition

A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a stable HIGH

level. This "START" condition must precede any command and initiate a data transfer onto the bus. The

device continuously monitors the SDA and SCL lines for a valid START and will not response to any com-

mand if this condition has not been met.

Stop Condition

A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at a stable

HIGH level. This condition terminates the communication between the devices and forces the bus inter-

face of the device into the initial condition.

Acknowledge

Indicates a successful data transfer. The transmitter will release the bus after sending 8 bits of data. Dur-

ing the 9th clock cycle the receiver will pull the SDA line to LOW level to indicate it received the eight bits

of data.

Data Transfer

During data transfer the device samples the SDA line on the leading edge of the SCL clock. Therefore, for

proper device operation the SDA line must be stable during the SCL LOW to HIGH transition.

Device Addressing

To start the communication between two devices, the bus master must initiate a start instruction se-

quence, followed by an eight bit word corresponding to the address of the device.

The device recognizes the following two addresses:

1100010d

tuner part address

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