www.ti.com

I/O Port

SDA

SCL

Start Condition

S

Stop Condition

P

PCA9536

WITH CONFIGURATION REGISTERS

SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak

pullup (100 k

Ω typ) to V

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In

applied to this I/O pin should not exceed the recommended levels for proper operation.

connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address

byte is sent, most-significant bit (MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse.

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (Start or Stop) (see Figure 2).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 1).

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see

Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,

the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold

times must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK)

after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line

high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

Figure 1. Definition of Start and Stop Conditions

4

Submit Documentation Feedback