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PCA9536DRG4 数据表(PDF) 5 Page - Texas Instruments |
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PCA9536DRG4 数据表(HTML) 5 Page - Texas Instruments |
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5 / 25 page ![]() www.ti.com SDA SCL Data Line Stable; Data Valid Change of Data Allowed Data Output by Transmitter SCL From Master Start Condition S 1 2 8 9 Data Output by Receiver Clock Pulse for Acknowledgment NACK ACK Device Address 1 0 Slave Address R/W Fixed 1 0 0 0 0 PCA9536 REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 Figure 2. Bit Transfer Figure 3. Acknowledgment on the I2C Bus Interface Definition BIT BYTE 7 (MSB) 6 5 4 3 2 1 0 (LSB) I2C slave address H L L L L L H R/W Does not affect operation of the PCA9536 Px I/O data bus P3 P2 P1 P0 P7 P6 P5 P4 Figure 4 shows the address byte of the PCA9536. Figure 4. PCA9536 Address 5 Submit Documentation Feedback |
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