Data Sheet

ADRF5700

APPLICATIONS INFORMATION

analog.com

Rev. 0 | 15 of 16

The ADRF5700 has two power supply pins (VDD and VSS) and six

control pins (LE, D2, D3, D4, D5, and D6). Figure 25 shows the

external components and connections for supply and control pins.

The VDD pin and the VSS pin are decoupled with a 100 pF multi-

layer ceramic capacitor. The device pinout allows the placement of

the decoupling capacitors close to the device. No other external

components are needed for bias and operation, except DC blocking

capacitors on the RFx pins when the RF lines are biased at a

voltage other than 0 V. For more details, see the Pin Configuration

and Function Descriptions section.

Figure 25. Recommended Schematic

RECOMMENDATIONS FOR PCB DESIGN

The RF ports are matched to 50 Ω internally, and the pinout

is designed to mate a coplanar waveguide (CPWG) with a 50

Ω characteristic impedance on the PCB. Figure 26 shows the

referenced CPWG RF trace design for an RF substrate with 12 mil

thick Rogers RO4003 dielectric material. The RF trace with a 16 mil

width and a 6 mil clearance is recommended for 2.2 mil finished

copper thickness.

Figure 26. Example PCB Stackup

Figure 27 shows the routing of the RF traces, supply, and control

signals from the device. The ground planes are connected with as

many filled through vias as allowed for optimal RF and thermal

performance. The primary thermal path for the device is the bottom

side.

Figure 27. PCB Routings

Figure 28 shows the recommended layout from the device RFx

pins to the 50 Ω CPWG on the referenced stackup. PCB pads are

drawn 1:1 to device pads. The ground pads are drawn solder mask

defined, and the signal pads are drawn as pad defined. The RF

trace from the PCB pad is extended with the same width up to the

package edge and tapered to the RF trace with a 45° angle. The

paste mask is also designed to match the pad without any aperture

reduction and is divided into multiple openings for the paddle.

Figure 28. Recommended RF Pin Transitions

For alternate PCB stackups with different dielectric thickness and

CPWG design, contact Technical Support for further recommenda-

tions.