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AM29DL800B 数据表(PDF) 34 Page - Advanced Micro Devices |
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AM29DL800B 数据表(HTML) 34 Page - Advanced Micro Devices |
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34 / 46 page ![]() 32 Am29DL800B 21519C4 December 4, 2006 D A TA SH EET AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter 70 90 120 JEDEC Std Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 45 45 50 ns tWLAX tAH Address Hold Time Min 45 45 50 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 35 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 20 25 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 35 50 ns tWHDL tWPH Write Pulse Width High Min 30 ns tSR/W Zero Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs Word Typ 11 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns |
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