AM29SL160C datasheet(20/52 Pages) AMD

20 / 52 page

Am29SL160C

21635C5 January 23, 2007

D A TA

SH EE T

Figure 2.

Temporary Sector Unprotect Operation

Secured Silicon (SecSi) Sector Flash

Memory Region

The Secured Silicon (SecSi) Sector is a flash memory

region that enables permanent part identification

through an Electronic Serial Number (ESN). The SecSi

Sector in this device is 256 bytes in length. The device

contains a SecSi Sector indicator bit that allows the

system to determine whether or not the SecSi Sector

was factory locked. This indicator bit is permanently set

at the factory and cannot be changed, which prevents

a factory-locked part from being cloned.

AMD offers this device only with the SecSi Sector

factory serialized and locked. The first sixteen bytes of

the SecSi Sector contain a random ESN. To utilize the

remainder SecSi Sector space, customers must

provide their code to AMD through AMD’s Express

Flash service. The factory will program and perma-

nently protect the SecSi Sector (in addition to

programming and protecting the remainder of the

device as required).

The system can read the SecSi Sector by writing the

Enter SecSi Sector command sequence (see “Enter

SecSi Sector/Exit SecSi Sector Command Sequence”

on page 22). Table 7, on page 18 shows the layout for

the SecSi Sector.

Table 7.

SecSi Sector Addresses

The device continues to read from the SecSi Sector

until the system issues the Exit SecSi Sector command

sequence, or until power is removed from the device.

On power-up, or following a hardware reset, the device

reverts to sending commands to the boot sectors.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadver tent writes (refer to Table 12, on

page 26 for command definitions). In addition, the fol-

lowing hardware data protection measures prevent

accidental erasure or programming, which might other-

wise be caused by spurious system level signals during

CC power-up and power-down transitions, or from

system noise.

Low VCC Write Inhibit

When V

CC is less than VLKO, the device does not accept

any write cycles. This protects data during V

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until V

is greater than V

LKO. The system must provide the

proper signals to the control pins to prevent uninten-

tional writes when V

CC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

IL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = V

IL and OE# = VIH during power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

START

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = V

(Note 1)

Notes:

1. All protected sectors unprotected. (If WP#/ACC = V

IL,

the outermost sectors remain protected)

2. All previously protected sectors are protected once

again.

Description

Address Range

Word Mode (x16) Byte Mode (x8)

16-byte random ESN

00–07h

000–00Fh

User-defined code or

factory erased (all 1s)

08–7Fh

010–0FFh

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