AM29SL160C datasheet(11/52 Pages) AMD

11 / 52 page

January 23, 2007 21635C5

Am29SL160C

D A TA

SH EE T

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state

machine. The state machine outputs dictate the func-

tion of the device. Table 1 lists the device bus

operations, the inputs and control levels they require,

and the resulting output. The following subsections

describe each of these operations in further detail.

Table 1.

Am29SL160C Device Bus Operations

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 10 ± 1.0 V, VHH = 10 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In,

DOUT = Data Out

Notes:

1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector/Sector

Block Protection and Unprotection” on page 15.

3. If WP#/ACC = VIL, the two outermost boot sectors are protected. If WP#/ACC = VIH, the two outermost boot sectors are

protected or unprotected as previously set by the system. If WP#/ACC = V

HH, all sectors, including the two outermost boot

sectors, are unprotected.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V

IL. CE# is the power

control and selects the device. OE# is the output

control and gates array data to the output pins. WE#

should remain at V

IH. The BYTE# pin deter mines

whether the device outputs array data in words or

bytes.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No

command is necessary in this mode to obtain array

Operation

CE#

OE# WE# RESET# WP#/ACC

Addresses

(Note 1)

DQ0–

DQ7

DQ8–DQ15

BYTE#

= V

BYTE#

= V

Read

AIN

DOUT

DQ8–DQ14 = High-Z,

DQ15 = A-1

Write

(Program/Erase)

(Note 3)

AIN

DIN

Standby

VCC ±

0.2 V

VCC ±

0.2 V

High-Z

Output Disable

High-Z

Reset

High-Z

Sector Protect

(Note 2)

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Unprotect

(Note 2)

(Note 3)

Sector Address,

A6 = H, A1 = H,

A0 = L

Temporary Sector

Unprotect

VID

(Note 3)

AIN

DIN

High-Z

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