AM29BL802CB datasheet(18/46 Pages) AMD

18 / 46 page

Am29BL802C

22371C7 November 3, 2006

D A TA

SH EET

Figure 4.

Burst Mode Read with 25 MHz CLK, 70 ns tIACC, 24 ns tBACC Parameters

Reset Command

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don’t care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

See “AC Characteristics” for parameters, and to Figure

17 for the timing diagram.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

Table 4 shows the address and data requirements. This

method is an alternative to that shown in Table 1, which

is intended for PROM programmers and requires VID

on address bit A9.

The autoselect command sequence is initiated by writ-

ing two unlock cycles, followed by the autoselect com-

mand. The device then enters the autoselect mode,

and the system may read at any address any number

of times, without initiating another command sequence.

A read cycle at address 00h retrieves the manufacturer

code. A read cycle at address 01h returns the device

code. A read cycle containing a sector address (SA)

and the address 02h in word mode returns 0001h if that

sector is protected, or 0000h if it is unprotected. Refer

to Table 2 for valid sector addresses. A read cycle at

address 03h returns 0000h if the device is in asynchro-

nous mode, or 0001h if in synchronous (burst) mode.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically gener-

ates the program pulses and verifies the programmed

cell margin. Table 4 shows the address and data re-

quirements for the program command sequence.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using DQ7,

DQ6, or RY/BY#. See “Write Operation Status” for in-

formation on these status bits.

CLK

LBA#

BAA#

Data

Step 1

Step 2

Step 3

40 ns

70 ns

40 ns

24 ns

Da +1

24 ns

Da +2

Da +3

24 ns

OE#

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