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AM29PDL127H 数据表(PDF) 53 Page - Advanced Micro Devices |
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AM29PDL127H 数据表(HTML) 53 Page - Advanced Micro Devices |
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53 / 68 page  June 07, 2005 Am29PDL127H 51 P RE L I M I NARY AC CHARACTERISTIC Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 11 and Table 16 for test specifications 3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to V CC/2 is taken as tDF. 4. For 70 pF output load capacitance, 2 ns will be added to t ACC, tCE, tPACC, tOE values for all speed options. Parameter Description Test Setup Speed Options JEDEC Std. 53 63 68 88 Unit tAVAV tRC Read Cycle Time (Note 1) Min 55 65 65 85 ns tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 55 656585ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max 60 657085ns tPACC Page Access Time Max 20 25 70 85 ns tGLQV tOE Output Enable to Output Delay Max 20 25 30 30 ns tEHQZ tDF Chip Enable to Output High Z (Note 3) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Notes 1, 3) Max 16 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Notes 3) Min 5 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns |
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