COM20020IP3V datasheet(39/82 Pages) SMSC

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Table 9 - Sub Address Register

BIT

BIT NAME

SYMBOL

DESCRIPTION

7-3

Reserved

These bits are undefined.

2,1,0

Sub Address 2,1,0

SUBAD

2,1,0

These bits determine which register at address 07 may be

accessed. The combinations are as follows:

SUBAD2

SUBAD1 SUBAD0

0 Tentative ID \ (Same

1 Node ID

\ as in

0 Setup 1

/ Config

1 Next ID

/ Register)

0 Setup 2

1 Reserved

0 Reserved

1 Reserved

SUBAD1 and SUBAD0 are exactly the same as exist in the

Configuration Register. SUBAD2 is cleared automatically by

writing the Configuration Register.

Table 10 - Configuration Register

Reset

RESET

A software reset of the COM20020 is executed by writing a

logic "1" to this bit.

A software reset does not reset the

microcontroller interface mode, nor does it affect the

Configuration Register. The only registers that the software

reset affect are the Status Register, the Next ID Register, and

the Diagnostic Status Register.

This bit must be brought

back to logic "0" to release the reset.

Command

Chaining Enable

CCHEN

This bit, if high, enables the Command Chaining operation of

the device. Please refer to the Command Chaining section

for further details. A low level on this bit ensures software

compatibility with previous SMSC ARCNET devices.

COM20020IP3V 数据表(PDF) 39 Page - SMSC Corporation

COM20020IP3V 数据表(HTML) 39 Page - SMSC Corporation

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