COM20020IP3V datasheet(70/82 Pages) SMSC

70 / 82 page

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FIGURE 17 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE

Data Hold from nWR High

nWR Low Width

nWR High Width

nRD

to nWR Low

A0-A2

VALID DATA

VALID

D0-D7

nCS

Note 2

nWR

nRD

t10

Note 3

t5**

t10

Parameter

Address Setup to nWR Active

nCS Setup to WR Active

Valid Data Setup to nWR High

min

max

4TARB

30***

units

nCS Hold from nWR Inactive

Address Hold from nWR Inactive

Cycle Time (nWR

to Next

)**

***:

nCS may become active after control becomes active, but the data setup time will n

be 30 nS measured from the later of nCS falling or Valid Data available.

The Microcontroller typically accesses the COM20020 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

Note 2: Any cycle occurring after a write to the Address Pointer Low Register

requires a minimum of 4TARB from the trailing edge of nWR to the leading edge

of the next nWR.

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

Write cycle for Address Pointer Low

egister occurring after a write to Data

COM20020IP3V 数据表(PDF) 70 Page - SMSC Corporation

COM20020IP3V 数据表(HTML) 70 Page - SMSC Corporation

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