PCD5002 datasheet(21/48 Pages) PHILIPS

21 / 48 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG and APOC-1 Paging

Decoder

PCD5002

Table 17 Status register (00H; read)

Note

1. After a status read operation bits D3, D4 and D7 are always reset, bits D1 and D0 only when no second call is

pending. D2 is reset when the RAM is empty (read and write pointers equal).

Table 18 Control register (00H; write)

BIT(1)

VALUE

DESCRIPTION

D1 and D0

0 0

no new call data

0 1

new call received (POCSAG or APOC-1)

1 0

continuous decoding data available

1 1

batch zero data available (APOC-1)

D3 and D2

0 0

no data to be read (default after reset)

0 1

RAM read/write pointers different; data to be read

1 0

RAM read/write pointers equal; no more data to read

1 1

RAM buffer full or overﬂow

alert time-out expired

out-of-range

BAT input HIGH or RXE output active (selected by control bit D2)

periodic timer interrupt

BIT (MSB: D7)

VALUE

DESCRIPTION

forced call termination (automatically reset after termination)

EEPROM programming enable

BAT input selected for monitoring (status bit D6)

RXE output selected for monitoring (status bit D6)

receiver continuously enabled (RXE = 1, ROE = 1)

decoder in OFF status (while DON = 0)

decoder in ON status

D5 to D7

not used: ignored when written

8.28

Pending interrupts

A secondary status register is used for storing status bits

of pending interrupts. This occurs:

• When a new call is received while the previous one was

not yet acknowledged by reading the status register

• When an interrupt occurs during a status read operation.

After completion of the status read the primary register is

loaded with the contents of the secondary register, which

is then reset. An immediate interrupt is then generated,

output INT becoming active 1 decoder clock cycle after it

was reset following the status read.

Remark: In the event of multiple pending calls, only the

status bits of the last call are retained.

8.29

Out-of-range indication

The out-of-range condition occurs when entering the

‘fade recovery’ or ‘carrier off’ mode in POCSAG, or

‘transmitter off’ or ‘carrier detect’ mode in APOC-1. This

condition is reflected in bit D5 of the status register.

The out-of-range condition is reset when either preamble

or a valid sync word is detected.

The out-of-range bit (D5) in the status register is updated

each time the receiver is disabled (RXE

↓ 0). Every

change of state in bit D5 generates an interrupt.

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