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PCD5002 数据表(PDF) 39 Page - NXP Semiconductors |
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PCD5002 数据表(HTML) 39 Page - NXP Semiconductors |
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39 / 48 page  1997 Jun 24 39 Philips Semiconductors Product specification Advanced POCSAG and APOC-1 Paging Decoder PCD5002 Notes 1. 32768 Hz reference signal; 32 pulses per 75 clock cycles, alternately separated by 1 or 2 pulse periods (pulse duration: tRFP). The timing is shown in Fig.15. 2. 50 Hz reference signal: square wave. 3. Duration depends on programmed bit rate; after reset tZSU = 1.5 bits. 4. Nominal values; pause in 12th data bit (see Table 11). POCSAG data timing (1200 bits/s) fDI data input rate SPF byte 01H; D5 = 1; D4 = 0 − 1200 − bits/s tBIT bit duration − 833.3 −µs tCW codeword duration − 26.7 − ms tPA preamble duration 480 −− ms tBAT batch duration − 453.3 − ms POCSAG data timing (2400 bits/s) fDI data input rate SPF byte 01H; D5 = 1; D4 = 1 − 2400 − bits/s tBIT bit duration − 416.6 −µs tCW codeword duration − 13.3 − ms tPA preamble duration 240 −− ms tBAT batch duration − 226.6 − ms APOC-1 batch timing tSB cycle duration SPF byte 00H; bit D2 = 0 (5 batches) − 2720 − bits SPF byte 00H; bit D2 = 0 (15 batches) − 8160 − bits Synthesizer control tZSU synthesizer set-up duration oscillator running; note 3 1 − 2 bits fZSC output clock frequency note 4 − 38400 − Hz tZCL clock pulse duration − 13.02 −µs tZSD data bit duration note 4 − 26.04 −µs tZDS data bit set-up time − 13.02 −µs tZDL1 data load enable delay − 91.15 −µs tZLE load enable pulse duration − 13.02 −µs tZDL2 inter block delay − 117.19 −µs SYMBOLS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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