PCD5002 datasheet(26/48 Pages) PHILIPS

26 / 48 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG and APOC-1 Paging

Decoder

PCD5002

8.44

RAM write address pointer (06H; read)

The RAM write address pointer is automatically

incremented during call reception, because the decoder

writes each data byte to RAM. The RAM write address

pointer can only be read. Values range from 00H to 5FH.

Bit D7 (MSB) is not used and its value is undefined when

read. When a call data byte is written to location 5FH, the

write address pointer wraps around to 00H. This does not

necessarily imply a RAM full condition.

8.45

RAM read address pointer (08H; read/write)

The RAM read address pointer is automatically

incremented after reading a data byte via the RAM output

The RAM read address pointer can be accessed for

reading and writing.

The values range from 00H to 5FH. When at 5FH a read

operation will cause wrapping around to 00H. Bit D7

(MSB) is not used; it is ignored when written to and

undefined when read from.

8.46

RAM data output register (09H; read)

The RAM data output register contains the byte addressed

by the RAM read address pointer and can only be read.

Each read operation causes an increment of the RAM read

address pointer.

8.47

EEPROM access

The EEPROM is intended for storage of user addresses

(RICs), sync words and special programmed function

(SPF) bits representing the decoder configuration.

The EEPROM can store 48 bytes of information and is

organized as a matrix of 8 rows by 6 columns.

The EEPROM is accessed indirectly via an address

pointer and a data I/O register.

The EEPROM is protected against inadvertent writing by

means of the programming enable bit in the control

The EEPROM memory map is non-contiguous. Figure 11

shows both the EEPROM organization and the access

method.

Identiﬁer locations contain RICs or sync words. A total of

20 unassigned bytes are available for general purpose

storage.

8.48

EEPROM address pointer (07H; read/write)

An EEPROM location is addressed via the EEPROM

address pointer. It is incremented automatically each time

a byte is read from or written to via the EEPROM data I/O

The EEPROM address pointer contains two counters for

the row and the column number. Bits D2 to D0 contain the

column number (0 to 5) and bits D5 to D3 the row number

(0 to 7). Bits D7 and D6 of the address pointer are not

used. Data written to these bits will be ignored, while their

values are undefined when read.

The column and row counters are connected in series.

Upon overflow of the column counter (column = 5) the row

counter is automatically incremented and the column

counter wraps to 0. On overflow the row counter wraps

from 7 to 0.

8.49

EEPROM data I/O register (0AH; read/write)

The byte addressed by the EEPROM address pointer can

be written to or read from via the EEPROM data I/O

EEPROM address pointer.

8.50

EEPROM access limitations

Since the EEPROM address pointer is used during data

decoding, the EEPROM may not be accessed while the

receiver is active (RXE = 1). It is advisable to switch to the

OFF state before accessing the EEPROM.

The EEPROM cannot be written to unless the EEPROM

programming enable bit (bit D1) in the control register is

set.

For writing a minimum programmed supply voltage (VPG)

is required (2.0 V typ.). The programmed supply current

(IPG) required during writing is approximately 500 µA.

8.51

EEPROM read operation

EEPROM read operations must start at a valid address in

the non-contiguous memory map. Single byte or block

reads are permitted.

8.52

EEPROM write operation

EEPROM write operations must always take place in

blocks of 6 bytes, starting at the beginning of a row.

Programming a single byte will reset the other bytes in the

same row. Modifying a single byte in a row requires

re-writing the unchanged bytes with their old contents.

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