Philips Semiconductors

PCF8563

Real-time clock/calendar

Product specification

16 April 1999

5 of 30

9397 750 04855

© Philips Electronics N.V. 1999. All rights reserved.

8.4 Reset

The PCF8563 includes an internal reset circuit which is active whenever the oscillator

the address pointer, are cleared with the exception of bits FE, VL, TD1, TD0, TESTC

and AE which are set to logic 1.

8.5 Voltage-low detector and clock monitor

VL bit (Voltage Low, bit 7 in the Seconds register) is set to indicate that reliable

clock/calendar information is no longer guaranteed. The VL flag can only be cleared

by software.

then the VL bit will be set. This will indicate that the time may be corrupted.

8.6 Register organization

Fig 4.

Voltage-low detection.

handbook, halfpage

VL set

normal power

operation

period of battery

operation

t

VDD

Vlow

MGR887

Table 4:

Registers overview

Bit positions labelled as ‘

−’are not implemented; those labelled with ‘0’ should always be written with logic 0.

Address Register name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00H

Control/Status 1

TEST1

0

STOP

0

TESTC

0

0

0

01H

Control/Status 2

0

0

0

TI/TP

AF

TF

AIE

TIE

0DH

CLKOUT frequency

FE

−−−−−

FD1

FD0

0EH

Timer control

TE

−−−−−

TD1

TD0

0FH

Timer countdown

value

<timer countdown value>