Philips Semiconductors

PCF8563

Real-time clock/calendar

Product specification

16 April 1999

13 of 30

9397 750 04855

© Philips Electronics N.V. 1999. All rights reserved.

8.9 Serial interface

8.9.1

modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both

lines must be connected to a positive supply via a pull-up resistor. Data transfer may

be initiated only when the bus is not busy.

message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device

that controls the message is the ‘master’ and the devices which are controlled by the

master are the ‘slaves’.

8.9.2

START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is defined as the start condition (S).

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the

stop condition (P); see Figure 7.

Fig 5.

POR override sequence.

handbook, full pagewidth

MGM664

SCL

500 ns

2000 ns

SDA

8 ms

override active

power up

Fig 6.

MBA605

MASTER

TRANSMITTER /

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER /

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER /

RECEIVER

SDA

SCL

Fig 7.

width

MBC622

SDA

SCL

P

STOP condition

SDA

SCL

S

START condition