PCF8573 datasheet(6/24 Pages) PHILIPS

6 / 24 page

1997 Mar 28

Philips Semiconductors

Product speciﬁcation

Clock/calendar with Power Fail Detector

PCF8573

7.5

Power on/power fail detection

If the voltage VDD − VSS1 falls below a certain value the

operation of the clock becomes undefined. Thus a warning

signal is required to indicate that faultless operation of the

clock is not guaranteed. This information is latched in a

flag called POWF (Power Fail) and remains latched after

restoration of the correct supply voltage until a write

procedure with EXECUTE ADDRESS has been received.

The flag POWF can be set by an internally generated

power fail level-discriminator signal for application with

(VDD − VSS1) greater than VTH1, or by an externally

generated power fail signal for application with

(VDD − VSS1) less than VTH1. The external signal must be

applied to the input PFIN. The input stage operates with

signals of slow rise and fall times. Internally or externally

controlled POWF can be selected by input EXTPF as

shown in Table 2.

Table 2

Power fail selection

Note

1. 0 = VSS1 (LOW); 1 = VDD (HIGH).

EXTPF(1)

PFIN(1)

FUNCTION

power fail is sensed internally

test mode

power fail is sensed externally

no power fail sensed

The external power fail control operates by absence of the

VDD − VSS2 supply. Therefore the input levels applied to

PFIN and EXTPF must be within the range of VDD−VSS1.

A LOW level at PFIN indicates a power fail. POWF is

readable via the I2C-bus. A power-on reset for the I2C-bus

control is generated on-chip when the supply voltage

VDD − VSS2 is less than VTH2.

7.6

Interface level shifters

The level shifters adjust the 5 V operating voltage

(VDD − VSS2) of the microcontroller to the internal supply

voltage (VDD − VSS1) of the clock/calendar. The oscillator

and counter are not influenced by the VDD − VSS2 supply

voltage. If the voltage VDD − VSS2 is absent (VDD =VSS2)

the output signal of the level shifter is HIGH because VDD

is the common node of the VDD − VSS2 and the VDD − VSS1

supplies. Because the level shifters invert the input

signals, the internal circuit behaves as if a LOW signal is

present on the inputs. FSET, SEC, MIN and COMP are

CMOS push-pull output stages. The driving capability of

these outputs is lost when the supply voltage

VDD − VSS2 =0.

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