1997 Mar 28

7

Philips Semiconductors

Product specification

Clock/calendar with Power Fail Detector

PCF8573

8

(SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when

connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

8.1

Bit transfer (see Fig.3)

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period

of the clock pulse as changes in the data line at this time will be interpreted as control signals.

8.2

Start and stop conditions (see Fig.4)

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the

clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is

defined as the stop condition (P).

Fig.3 Bit transfer.

MBC621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig.4 Definition of start and stop conditions.

MBC622

SDA

SCL

P

STOP condition

SDA

SCL

S

START condition