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PCF8573 数据表(PDF) 16 Page - NXP Semiconductors |
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PCF8573 数据表(HTML) 16 Page - NXP Semiconductors |
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16 / 24 page  1997 Mar 28 16 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector PCF8573 13 AC CHARACTERISTICS VSS2 =0V; Tamb = −40 to +85 °C unless otherwise specified. Typical values at Tamb = +25 °C. Notes 1. All timing values are valid within the operating supply voltage and ambient temperature range and reference to VIL and VIH with an input voltage swing of VSS to VDD. 2. A detailed description of the I2C-bus specification, with applications, is given in brochure “The I2C-bus and how to use it”. This brochure may be ordered using the code 9398 393 40011. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Rise and fall times of input signals tr rise time input EXTPF −− 1 µs input PFIN −−∞ µs all other inputs (levels between VIL and VIH) −− 1 µs tf fall time input EXTPF −− 1 µs input PFIN −−∞ µs all other inputs (levels between VIL and VIH) −− 0.3 µs Oscillator Cosc integrated oscillator capacitance − 40 − pF Rf oscillator feedback resistance − 3 − M Ω ∆fosc oscillator stability ∆(VDD − VSS1) = 100 mV; Tamb =25 °C; (VDD − VSS1) = 1.55 V − 2 × 10−7 − Quartz crystal parameters (f = 32.768 kHz) Rs series resistance −− 40 k Ω CL parallel load capacitance − 10 − pF CT trimmer capacitance 5 − 25 pF I2C-bus timing (see Fig.12; notes 1 and 2) fSCL SCL clock frequency −− 100 kHz tSP tolerable spike width on bus −− 100 ns tBUF bus free time 4.7 −−µs tSU;STA START condition set-up time 4.7 −−µs tHD;STA START condition hold time 4.0 −−µs tLOW SCL LOW time 4.7 −−µs tHIGH SCL HIGH time 4.0 −−µs tr SCL and SDA rise time −− 1.0 µs tf SCL and SDA fall time −− 0.3 µs tSU;DAT data set-up time 250 −− ns tHD;DAT data hold time 0 −− ns tVD;DAT SCL LOW to data out valid −− 3.4 µs tSU;STO STOP condition set-up time 4.0 −−µs |
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