PCF8574TS datasheet(7/24 Pages) PHILIPS

7 / 24 page

1997 Apr 02

Philips Semiconductors

Product speciﬁcation

Remote 8-bit I/O expander for I2C-bus

PCF8574

6.4

Acknowledge

The number of data bytes transferred between the start

and the stop conditions from transmitter to receiver is not

limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put

on the bus by the transmitter whereas the master

generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an

acknowledge after the reception of each byte. Also a

master must generate an acknowledge after the reception

of each byte that has been clocked out of the slave

transmitter. The device that acknowledges has to pull

down the SDA line during the acknowledge clock pulse, so

that the SDA line is stable LOW during the HIGH period of

the acknowledge related clock pulse, set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the

transmitter by not generating an acknowledge on the last

byte that has been clocked out of the slave. In this event

the transmitter must leave the data line HIGH to enable the

master to generate a stop condition.

Fig.7 Acknowledgment on the I2C-bus.

MBC602

START

CONDITION

clock pulse for

acknowledgement

not acknowledge

acknowledge

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

PCF8574TS 数据表(PDF) 7 Page - NXP Semiconductors

PCF8574TS 数据表(HTML) 7 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

数据表下载