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PCF8574TS 数据表(PDF) 14 Page - NXP Semiconductors |
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PCF8574TS 数据表(HTML) 14 Page - NXP Semiconductors |
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14 / 24 page ![]() 1997 Apr 02 14 Philips Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 Note 1. The Power-on reset circuit resets the I2C-bus logic with VDD <VPOR and sets all I/Os to logic 1 (with current source to VDD). I/Os VIL LOW level input voltage −0.5 − +0.3VDD V VIH HIGH level input voltage 0.7VDD − VDD + 0.5 V IIHL(max) maximum allowed input current through protection diode VI ≥ VDD or VI ≤ VSS −− ±400 µA IOL LOW level output current VOL =1V; VDD =5V 10 25 − mA IOH HIGH level output current VOH =VSS 30 − 300 µA IOHt transient pull-up current HIGH during acknowledge (see Fig.14); VOH =VSS; VDD = 2.5 V −−1 − mA Ci input capacitance −− 10 pF Co output capacitance −− 10 pF Port timing; CL ≤ 100 pF (see Figs 10 and 11) tpv output data valid −− 4 µs tsu input data set-up time 0 −− µs th input data hold time 4 −− µs Interrupt INT (see Fig.13) IOL LOW level output current VOL = 0.4 V 1.6 −− mA IL leakage current VI =VDD or VSS −1 − +1 µA TIMING;CL ≤ 100 PF tiv input data valid time −− 4 µs tir reset delay time −− 4 µs Select inputs A0 to A2 VIL LOW level input voltage −0.5 − +0.3VDD V VIH HIGH level input voltage 0.7VDD − VDD + 0.5 V ILI input leakage current pin at VDD or VSS −250 − +250 nA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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