PCF8577CUSLASH10 datasheet(10/28 Pages) PHILIPS

10 / 28 page

1998 Jul 30

Philips Semiconductors

Product speciﬁcation

LCD direct/duplex driver with

I2C-bus interface

PCF8577C

CHARACTERISTICS OF THE I2C-BUS

The I2C-bus is for 2-way, 2-line communication between

different ICs or modules. The two lines are a serial data

line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when

connected to the output stages of a device. Data transfer

may be initiated only when the I2C-bus is not busy.

7.1

Bit transfer

One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during the

HIGH period of the clock pulse as changes in the data line

at this time will be interpreted as control signals.

7.2

Start and stop conditions

Both data and clock lines remain HIGH when the I2C-bus

is not busy. A HIGH-to-LOW transition of the data line,

while the clock is HIGH is defined as the start condition (S).

A LOW-to-HIGH transition of the data line while the clock

is HIGH is defined as the stop condition (P).

7.3

System conﬁguration

A device generating a message is a ‘transmitter’, a device

receiving a message is the ‘receiver’. The device that

controls the message is the ‘master’ and the devices which

are controlled by the master are the ‘slaves’.

7.4

Acknowledge

The number of data bytes transferred between the start

and stop conditions from transmitter to receiver is not

limited. Each byte is followed by one acknowledge bit.

The acknowledge bit is a HIGH level put on the I2C-bus by

the transmitter whereas the master generates an extra

acknowledge related clock pulse. A slave receiver which is

addressed must generate an acknowledge after the

reception of each byte. Also a master must generate an

acknowledge after the reception of each byte that has

been clocked out of the slave transmitter. The device that

acknowledges has to pull down the SDA line during the

acknowledge clock pulse, set-up and hold times must be

taken into account. A master receiver must signal an end

of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of

the slave. In this event the transmitter must leave the data

line HIGH to enable the master to generate a stop

condition.

Fig.8 Bit transfer.

MBA607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

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