Philips Semiconductors

Preliminary specification

PCK2011

Direct Rambus

™ Clock Generator

1999 Jan 19

5

Power Management Modes

The DRCG device has three operating states: NORMAL, CLKSTOP

and POWERDOWN. In Normal mode, the clock source is on, and

the output is enabled. In CLKSTOP mode, the clock source is on,

but the output is disabled (STOPB deasserted). In Powerdown

mode, the device is powered down with the control signal PwrDnB

equal to 0. The control signals Mult0, Mult1, S0, S1 and S2 must be

stable before power is applied to the device, and can only be

changed in Power-down mode (PWRDNB=0).

Table 2. POWER MANAGEMENT MODES

MODE

PwrDnB

StopB

Clk

ClkB

NORMAL

1

1

PACLK

PACLKB

CLKSTOP

1

0

POWERDOWN

0

X

GND

GND

Upon applying power to the device, the device can enter any state,

depending on the settings of the control signals, PwrDnB and StopB.

The clock source output need not be glitch-free during state

transitions.

SW00360

DRCG

B

A

PPL

X

PWRDNB

S0

S1

S2

STOPB

CLK

CLKB

PACLK

PHASE

ALIGNER

ΦD

SYNCLKN

PCLKM

2

MULT

0

MULT

1

REFCLK

PLLCLK

TEST MUX

BYPASS MUX

BYPCLK

Figure 2. Direct Rambus Clock Generator Package