Philips Semiconductors

Preliminary specification

PCK2011

Direct Rambus

™ Clock Generator

2

1999 Jan 19

Overview

The Direct Rambus Clock Generator (DRCG) provides the Channel

clock signals for a Direct Rambus memory subsystem. It includes

signals to synchronize the Direct Rambus Channel clock to an

external system clock. Contained in a 24-pin SSOP package, the

DRCG provides an off-the-shelf solution for a broad range of Direct

Rambus memory applications.

Features

Provides a 400MHz differential clock source for Direct Rambus

memory systems for an 800MHz data transfer rate.

The DRCG includes signals to synchronize the clock domains of

the Rambus

R Channel with an external system or processor

clock.

The DRCG is able to turn off the Rambus Channel clock to

minimize power for mobile and other power-sensitive applications:

- In the “clock off” mode, the DRCG remains on while the output

is disabled, allowing fast transitions between the clock-off and

clock-on states. This mode could be used in conjunction with

the Nap mode of the RDRAMs and Rambus ASIC Cell (RAC).

- In the “power down” mode, the DRCG is completely powered

down for minimum power dissipation. This mode is used in

conjunction with the power down modes of the RDRAMs and

RAC.

The DRCG supports systems that do not require synchronization

of the Rambus clock to another system clock.

Synthesizer/Driver specification.

PIN CONFIGURATION

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

VDDLR

S0

REFCLK

S1

VDDP

VDDO

GNDP

GNDO

GNDl

CLK

PCLKM

N/C

SYNCLKN

CLKB

GNDC

VDDO

VDDC

GNDO

VDDIPD

MULT0

STOPB

MULT1

S2

SW00289

PWRDNB

Related Documentation

Direct Rambus RAC Overview

Direct Rambus Memory Controller Guide

Pin-outs

The DRCG is packaged in a 24-pin 150 mil SSOP. The pin

configuration shows the preliminary pin-out. Table 1 describes the

function and connection of each pin.

Example System Clock Configuration

Figure 2 shows the clocking configuration for an example Direct

Rambus subsystem. The configuration shows the interconnection of

the system clock source, the Direct Rambus Clock Generator

(DRCG), and the clock signals of a memory controller ASIC. The

ASIC contains the RAC, the Rambus Memory Controller protocol

engine (RMC), and logic to support synchronizing the Channel clock

with the controller clock. (This diagram represents the differential

clocks as a single Busclk wire.)

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DRAWING NUMBER

24-Pin Plastic SSOP

0

°C to +70°C

PCK2011 DL

PCK2011 DL

SOT340-1