Philips Semiconductors

Preliminary specification

PCK2011

Direct Rambus

™ Clock Generator

1999 Jan 19

8

Table 4. AC DEVICE CHARACTERISTICS

Symbol

Parameter

Min

Max

Unit

Clock cycle time

2.5

3.75

ns

Cycle-to-cycle jitter at Clk/ClkB

–

60

ps

–

100

ps

Phase Aligner phase step size (at Clk/ClkB)

1

–

ps

Phase Detector phase error for distributed loop Measured at PclkM-SynClkN (rising edges) (does not

include clock jitter)

– 100

100

ps

PLL output Phase error when tracking SSC

– 100

100

ps

DC

Output duty cycle over 10,000 cycles

40%

60%

Output cycle-to-cycle duty cycle error

–

50

ps

Output rise and fall times (measured at 20% – 80% of output voltage)

250

500

ps

Difference between rise and fall times on a single device (20% – 80%)

–

100

ps

Output voltage during Clkstop (StopB = 0)

1.1

2.0

V

Differential output crossing-point voltage

1.3

1.8

V

Output voltage swing (p-p single-ended)

0.4

0.6

V

Output HIGH voltage

–

2.0

V

Output LOW voltage

1.0

–

V

Output dynamic resistance (at pins)

12

50

Ω

Output current during Hi-Z (S0 = 0, S1 = 1)

–

50

µA

Output current during ClkStop (StopB = 0)

–

500

µA

Current on powerdown (PwrDnB = 0)

–

200

µA

Current on ClkStop (StopB = 0)

50

mA

Current on normal state (StopB = 1)

100

mA

NOTE:

Table 5. DRCG FUNCTIONS

REFCLK

MULT0

MULT1

PLL

CLK/CLKB

MODE

S0

S1

S2

CLK

CLKB

pin2

pin15

pin14

multiplier

pins 20/18

pin 24

pin 23

pin 13

pin 20

pin 18

33

1

1

8

267

Normal

0

0

0

PAclk

PAclk

50

0

1

6

300

Bypass

1

0

0

PLLclk

PLLclk

50

1

1

8

400

Test

1

1

0

Refclk

Refclk

67

0

0

4

267

Vendor Test A

0

0

1

–

–

67

0

1

6

400

Vendor Test B

1

0

1

–

–

100

1

0

8/3

267

Reserved

1

1

1

–

–

Output Test

0

1

x

Hi-Z

Hi-Z