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ADC3683 数据表(PDF) 21 Page - Texas Instruments

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部件名 ADC3683
功能描述  ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC
PDF  70 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

ADC3683 数据表(HTML) 21 Page - Texas Instruments

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7.3.2.2 Signal Acquisition Time Adjust
The ADC3683-SP includes a register (DLL PDN (0x11, D2) which increases the signal acquisition time window
for clock rates below 30 MSPS from 25% to 50% of the clock period. Increasing the sampling time provides
a longer time for the driving amplifier to settle out the signal which can improve the SNR performance of the
system. When powering down the DLL, the acquisition time tracks the clock duty cycle (50% is recommended).
Table 7-1. Acquisition time vs DLL PDN setting
SAMPLING CLOCK FS (MSPS)
DLL PDN (0x11, D2)
ACQUISITION TIME (tACQ)
65
0
TS / 4
≤ 30
1
TS / 2
www.ti.com
ADC3683-SP
SBASAB5 – MARCH 2024
Copyright © 2024 Texas Instruments Incorporated
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