TSL25713 datasheet(22/39 Pages) OSRAM

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ams Datasheet

Page 21

[v1-01] 2018-Mar-27

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TSL2571 − Register Description

ALS Timing Register (0x01)

The ALS timing register controls the internal integration time

of the ALS ADCs in 2.72-ms increments.

Figure 23:

ALS Timing Register

Wait Time Register (0x03)

Wait time is set 2.72 ms increments unless the WLONG bit is

asserted in which case the wait times are 12

× longer. WTIME is

programmed as a 2’s complement number.

Figure 24:

Wait Time Register

Note(s):

1. The Wait Time Register should be configured before AEN is asserted.

Field

Bits

Description

ATIME

7:0

VALUE

INTEG_CYCLES

TIME

MAX COUNT

0xFF

2.72 ms

1024

0xF6

27.2 ms

10240

0xDB

101 ms

37888

0xC0

174 ms

65535

0x00

256

696 ms

65535

Field

Bits

Description

WTIME

7:0

VALUE

WAIT TIME

TIME (WLONG = 0)

TIME (WLONG = 1)

0xFF

2.72 ms

0.032 s

0xB6

201 ms

2.4 s

0x00

256

696 ms

8.3 s

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