AD8146/AD8147/AD8148

Rev. 0 | Page 19 of 24

AD8146

CROSSPOINT SWITCH

54.9Ω

54.9Ω

1kΩ

1kΩ

500Ω

500Ω

INPUT I, NEGATIVE PHASE

INPUT I, POSITIVE PHASE

INPUT J, NEGATIVE PHASE

INPUT J, POSITIVE PHASE

INPUT K, NEGATIVE PHASE

INPUT K, POSITIVE PHASE

10Ω

10Ω

RED

CHANNEL

100Ω

UTP

54.9Ω

54.9Ω

1kΩ

1kΩ

500Ω

500Ω

10Ω

10Ω

GREEN

CHANNEL

100Ω

UTP

54.9Ω

54.9Ω

1kΩ

1kΩ

500Ω

500Ω

10Ω

10Ω

BLUE

CHANNEL

100Ω

UTP

VPOS = +2.5V

VNEG = –2.5V

Figure 35. Using the AD8146 as a Differential Receiver

Terminations are not required between the AD8146 and the

switch if the interconnection lengths are kept short (less than

two inches). The 10 Ω series resistors buffer the input

capacitance of the switch (typically 2 pF) and produce a low-

pass rolloff that is down by only 0.025 dB at 600 MHz.

OUTPUT PULL-DOWN (OPD)

The output pull-down feature, when used in conjunction with

series Schottky diodes, offers a convenient means to multiplex a

number of driver outputs together to form a video network. The

OPD pin is a binary input that controls the state of the outputs.

Its binary input level is referenced to GND (see the Specifications

section for the logic levels). When the OPD input is driven to its

low state, the output is enabled and operates in normal fashion.

bias on the series diodes, allowing the drivers to transmit

signals over the network. When the OPD input is driven to its

high state, the outputs of the drivers are forced to a low voltage,

series diodes and thus presenting high impedance to the

network. This feature allows a three-state output to be realized

that maintains its high impedance state even when the drivers

are not powered.

It is recommended that the output pull-down feature only be

used in conjunction with series diodes in such a way as to

ensure that the diodes are reverse-biased when the output pull-

down feature is asserted, because some loading conditions can

prevent the output voltage from being pulled all the way down.

LAYOUT AND POWER SUPPLY DECOUPLING

CONSIDERATIONS

Standard high speed PCB layout practices should be adhered

to when designing with the drivers. A solid ground plane is

required and good wideband power supply decoupling

networks should be placed as close as possible to the supply

pins. Small surface-mount ceramic capacitors are recommended

for these networks, and tantalum capacitors are recommended

for bulk supply decoupling.

Source termination resistors on the differential outputs must be

placed as close as possible to the output pins to minimize load

capacitance due to the PCB traces.

DRIVING A CAPACITIVE LOAD

A purely capacitive load can react with the output impedance

of any amplifier to produce an undesirable phase shift, which

reduces phase margin and results in high frequency ringing in

the pulse response. The best way to minimize this effect is to

place a small resistor in series with each of the outputs of the

amplifier to buffer the load capacitance. Most applications

include 49.9 Ω source termination resistors, which effectively

buffer any stray load capacitance.